Polycrystalline silicon (polysilicon) gates and interconnecting conductor lines for MOS and MNOS integrated circuits have, for more than a decade, replaced the more conventional metal gates and allowed for an additional set of conductive lines. Polysilicon has been found to be a particularly attractive material since it is very stable at the high temperatures necessary for introducing impurities in source and drain regions of semiconductor devices, can be oxidized to form a silicon dioxide thereon and is suitable for etching fine lines.
One disadvantage of polysilicon is its relatively high electrical resistance of the order of (20-30) ohms per square for a typical film of about 5000 Angstroms thickness. This high electrical resistance introduces RC time delays, particularly when the polysilicon lines are long. For example, at the device level, a 1 micron wide, 100 micron long line would have an RC time constant of about 0.1 ns. Correspondingly, rise-time would be 0.2 ns which is small compared to a 1 micron gate width device's intrinsic delay of 0.5 ns (fan-out of 2). But as polysilicon lines get longer--as in the word lines of large static or dynamic RAMs--the RC time delay can become the dominant speed limitation. Since this delay is proportional to the square of line length (both R and C vary linearly), the resistance of a 1000 micron line would cause a time delay of nearly 20 ns, which is significantly greater than device delays.
The above RC time delays in polysilicon are intolerable in present-day integrated circuits, particularly the very large scale integrated (VLSI) circuits, where high speed is an important requirement.
A number of alternatives to conventional polysilicon gates and interconnects exist. One alternative is the two-layer metal approach which substitutes metal for polysilicon in long lines where RC delay is likely to be a problem. An alternative to this first approach, is running a metal line parallel to a polysilicon line and strapping the two lines together at every few hundred microns or so. But this 2-layer metal approach is rather difficult to implement, not only from a device standpoint, especially in the case of VLSI's submicron layouts, but also from a process standpoint because the metals need to be isolated from each other.
A second alternative is to replace the polysilicon with a refractory metal silicide such as molybdenum silicide, tungsten silicide, tantalum silicide, titanium silicide and mixtures thereof. The silicides have processing properties similar to polysilicon with the added advantage of an order-of-magnitude lower sheet resistance. However, the silicide-gate designs have stability problems. If a silicide material is placed directly over the gate oxide, high temperature processing can cause the metal to diffuse through the gate and degrade the device performance via the gate oxide breakdown. Other problems with this approach include a high silicide to n.sup.+ -contact (or buried contact) resistance and the inability of the silicide to self-oxidize.
A third alternative that potentially avoids the metal diffusion problem is the use of a gate sandwich structure consisting of polysilicon on the bottom and a metal silicide on the top with only the polysilicon contacting the gate oxide. This polysilicon-silicide structure is commonly called a polycide. This approach offers the advantage of lower sheet resistance on the order of (1-5) ohms per square and is attractive from a process standpoint since it is more easily inserted into an existing process line. Because of these advantageous features, this approach has been gaining wide-spread popularity.
A number of polycide structures have been reported in the prior art. These include silicides of almost all the transition metals, chromium, nickel and iron formed on polysilicon. Of these, a tungsten polycide structure consisting of tungsten disilicide (WSi.sub.2) on top of a doped polysilicon layer has been the subject of intensive investigation not only because of its low resistivity but also because of its stable chemical processing properties and compatibility as a gate material (i.e. MOS devices fabricated with WSi.sub.2 /polysilicon gate material exhibit excellent silicon dioxide-silicon interface properties such as low surface state density, Q.sub.ss, and low surface state density distribution) while preserving the proven polysilicon gate advantages.
Methods of forming silicide, in particular tungsten silicide, on polysilicon are known to the prior art. For example, in U.S. Pat. No. 4,180,596 entitled "Method For Providing A Metal Silicide Layer On A Substrate" and issued on Dec. 25, 1979, to Crowder et al., is disclosed a method of forming a metal silicide such as molybdenum silicide, tantalum silicide, rhodium silicide and tungsten silicide on a substrate such as doped silicon or polysilicon. The silicide is formed by co-evaporation of silicon and the metal. Due to differences in evaporation rates of silicon and the metal, Crowder et al. employs a separate electron beam gun for evaporating these materials. The metal silicide films formed in this manner contain (25-60) atomic percent of the metal and (75-40) atomic percent of silicon.
However, the dual electron-beam co-evaporation technique of Crowder et al. suffers from a number of disadvantages. In particular, this process requires accurate and careful control (by means of a microprocessor controlled feedback circuit coupled to the evaporator) of each electron beam that impinges on the material and causes evaporation thereof to obtain stoichiometric WSi.sub.2. Another disadvantage of this prior art process is that the silicon material is rather difficult to evaporate using an electron beam since it requires a very high temperature to undergo the required phase change and the high temperature, in turn, causes large thermal gradients in the evaporator hearth, thereby producing "spitting" of the silicon. Consequently, the composition of the resulting tungsten silicide is uncertain.
Reference is now made to U.S. Pat. No. 4,285,761 entitled "Process For Selectively Forming Refractory Metal Silicide Layers On Semiconductor Devices" and issued Aug. 25, 1981 to Fatula et al. The Fatula et al. patent while teaching, like the Crowder et al. patent, a method of co-evaporation of a metal and silicon by heating the respective targets of metal and silicon with electron beams, suggests alternate techniques of evaporating a metal silicide on polysilicon. These suggested techniques are RF sputtering the metal silicide from a single target containing the right proportion of silicon and metal and also sputtering from two targets of the elemental metal and the elemental silicon. Forming the metal silicide by sputtering from a single target as suggested by Fatula et al. has two major drawbacks. Due to interaction between the target's constituents (i.e. the metal and the silicon) during sputtering the silicide film formed will not have the desired composition. Another problem is that the resulting silicide will receive large tensile stresses in the range (1-3).times.10.sup.10 dynes per square cm. due to volume shrinkage associated with their formation. As a result, the film will not be stable. Also, the silicide film suffers from cracking and peeling during subsequent process steps such as annealing and etching. Another problem is that a polycide gate formed by this process will have significant step coverage and reliability problems due to severe undercutting of the polysilicon during etching of the polycide layer to form the gate. Co-sputtering from two different targets of metal and silicon as suggested by Fatula et al., on the other hand, requires microprocessor-controlled power supplies for the individual targets to control the sputter rate from each target to provide the proper silicide composition. This necessitates an extensive and expensive modification of the sputtering system.
What is needed is a simple, inexpensive and dependable technique of forming metal silicides.
Accordingly, it is an object of the present invention to provide a process, which is particularly suited for a large volume manufacturing environment, of forming metal silicides by using an off-the-shelf sputter deposition system without the necessity for any modification thereof.
It is another object of this invention to provide a process of forming a metal silicide film on a polysilicon film that adheres excellently to the polysilicon enabling excellent electrical contact between the two films.
It is another object of this invention to provide a process which guarantees consistently silicon-rich metal silicide films.
It is yet another object of this invention to provide a process for forming a metal silicide film of high integrity suitable for gates and interconnecting conductor lines.
These and other objects of this invention will be apparent from the following description.